5 and 7 Nanometer Process. Who did it first? Who owns the technology?

#1
@Sambamba lets look at your beloved printing or photolithography.

After designing the chip it is then printed. I looked at the printer maker in Holland, ASML Holding and a keen look shows that it is controlled and financed by the usual U.S companies : IBM, Apple, Intel and then you have Samsung and TSMC.

ASML make the printing machines for these companies above according to the designs they need. And Trump has stopped ASML from selling machines to China :

https://www.reuters.com/article/us-asml-holding-usa-china-insight-idUSKBN1Z50HN


Looking at 7 nanometer which you love so much, si naona ni IBM ndio iliunda!

It then flows from IBM to the rest of the companies e.g TSMC but the U.S companies own the science and the patents.

https://en.m.wikipedia.org/wiki/7_nm_process




HistoryEdit
Technology demosEdit

7 nm scale MOSFETs were first demonstrated by researchers in the early 2000s. In 2002, an IBM research team including Bruce Doris, Turkish engineer Omer Dokumaci, Taiwanese engineer Meikei Ieong and Romanian engineer Anda Mocuta fabricated a 6 nm silicon-on-insulator (SOI) MOSFET.[6][7] In 2003, NEC's research team led by Hitoshi Wakabayashi and Shigeharu Yamagami fabricated a 5 nm MOSFET.[8][9]

In July 2015, IBM announced that they had built the first functional transistors with 7 nm technology, using a silicon-germanium process.[10][11][12][13]

In June 2016, TSMC had produced 256 Mbit SRAM memory cells at their 7 nm process,[1] with a cell area of 0.027 mm2 (550 F2) with reasonable risk production yields.[14]





Looking at 5 Nanometer printing, again you see the same old names. No mention of China or Huawei :

https://en.m.wikipedia.org/wiki/5_nm_process



Technology demosEdit
Single-transistor devices below 7 nm were first demonstrated by researchers in the early 2000s. In 2002, an IBM research team including Bruce Doris, Omer Dokumaci, Meikei Ieong and Anda Mocuta fabricated a 6-nanometre silicon-on-insulator (SOI) MOSFET.[9][10]

In 2003, a Japanese research team at NEC, led by Hitoshi Wakabayashi and Shigeharu Yamagami, fabricated the first 5 nm MOSFET.[11][12]

In 2015, IMEC and Cadence had fabricated 5 nm test chips. The fabricated test chips are not fully functional devices but rather are to evaluate patterning of interconnect layers.[13][14]

In 2015, Intel described a lateral nanowire (or gate-all-around) FET concept for the 5 nm node.[15]

In 2017, IBM revealed that they had created 5 nm silicon chips,[16] using silicon nanosheets in a gate-all-around configuration (GAAFET), a break from the usual FinFET design. The GAAFET transistors used had 3 nanosheets stacked on top of each other, covered in their entirety by the same gate, just like FinFETs usually have several physical fins side by side that are electrically a single unit and are covered in their entirety by the same gate. IBM's chip measured 50 mm2 and had 600 million transistors per mm2.[17][18]
 
#2
IBM announces 7 Nanometer Process to the world back in 2017 ....

https://www.ibm.com/blogs/research/2017/02/ibm-spie-seven-advancements-beyond-7nm-chips/




IBM at SPIE: Seven Advancements for Beyond 7nm Chips



February 27, 2017 | Written by: IBM Research Editorial Staff
Categorized: Materials Science | Nanotechnology | Systems
Share this post:



When we announced the industry’s first functional 7 nanometer node (7nm) test chips in 2015, with our GLOBALFOUNDRIES and Samsung partners, we knew the process for the chips to reach “manufacturing maturity” – perhaps as early as next year, would be rapid. As that effort accelerates in the semiconductor industry, IBM continues to push the boundary by focusing on the challenges of the next nodes beyond 7nm.

Our IBM team is presenting seven papers at this week’s 2017 International Society for Optics and Photonics (SPIE) Advanced Lithography conference focused on technology exploration and enablement beyond the 7nm node. And it starts with Extreme Ultraviolet (EUV) Lithography.

With 7nm chips, we’re now creating designs relating to a transistor’s size, or even the wiring between transistors, that are truly at the atomic level. To achieve this kind of scaling without overly-complex patterning schemes, EUV is key. In a single exposure, EUV can create a high-resolution pattern that is unattainable by prior semiconductor patterning processes. However, enabling EUV patterning requires specialized equipment, process, and know-how, all found at IBM’s research labs in Albany, NY and Yorktown Heights, NY. These seven advances presented at SPIE relating to EUV masks (templates used to print circuit designs onto a silicon wafer), and patterning materials (light-activated “resists” or etch-resistant materials), can all be seen as critical in enabling 7nm technology and beyond:

In Design intent optimization at the beyond 7nm node: The intersection of DTCO and EUVL stochastic mitigation techniques, Michael Crouse shows that even though the title of his talk is big, small changes in wiring designs can drastically improve printing conditions. In Figure 1, he shows that if the optimization of mask shapes is done correctly, continuous lines without breakage can be printed at the smallest dimensions required for the 7nm node and beyond.


Figure 1: Contrast optimization improvement on two-dimensional metal wiring demonstrated with EUV lithography. With the type of improvement illustrated on the right, features 20-30{ccf696850f4de51e8cea028aa388d2d2d2eef894571ad33a4aa3b26b43009887} smaller than those from the 7nm node can be more robustly printed, and physical/electrical variability can be drastically reduced.
In Investigation of alternate mask stacks in EUV lithography, Martin Burkhardt simulates the performance of new materials not being used currently for EUV masks. By considering the whole periodic table, he is able to illustrate that EUV masks which provide even better contrast are within our grasp. Actually fabricating masks with some of these materials would allow for higher fidelity patterns on a silicon wafer without any further change in EUV technology, and thus allow the industry to scale easily beyond 7nm.

In Comprehensive analysis of line-edge and line-width roughness for EUV lithography, Ravi Bonam illustrates how small imperfections and wiggles in a wiring line can be characterized clearly, and in doing so shows which conditions produce the straightest features, critical for improving manufacturability of the EUV patterning process, and the performance and yield of the chip.

In Fundamentals of EUV resist-inorganic hardmask interactions, Dario Goldfarb looks to improve the patterning material film stack (the point of transfer from pattern to wafer) by improving the physical and chemical interactions at the interfaces between these films, which often don’t like to stick to each other. He harnesses this understanding to create specific chemical interactions to hold these materials together (shown in Figure 2), which is critical to ensuring these tiny, EUV-patterned shapes are able to stay in place long enough to transfer their patterns into the substrate below.


Figure 2: An EUV resist that was previously impossible to pattern on an inorganic silicon hardmask can now be clearly patterned after surface customization tailored to the resist/hardmask combination.
In a similar theme to Dario Goldfarb’s talk, Indira Seshadri demonstrates in Ultrathin EUV patterning stack using polymer brush as an adhesion promotion layer, that by employing a polymer-like material that bridges between tiny EUV-patterned features and the underlying substrate, these very high-resolution patterns can be etched into the substrate below and retain the intended design shape, key to ensuring yieldable chips at these length scales.

With so many new thin-film solutions in play, the ability to discern and improve manufacturing-worthy processes early in the research phases is key. In a talk entitled Driving down defect density in composite EUV patterning film stacks, Luciana Meli demonstrates systematic case studies, using a hybrid of available defect inspection techniques, to show the process and materials improvements necessary to deliver the low defectivity required for 7nm and beyond EUV manufacturability.

Bringing many of these concepts of imaging and materials improvements together, Anuja De Silva will present a talk entitled Single-expose patterning development for EUV lithography, showcasing successful patterning of wiring circuits at the dimensions of 30nm and below required beyond the 7nm node. The ability to achieve this represents a large leap from the capabilities first available for the 7nm node (see Figure 3), and can actually improve the 7nm node itself, though she will highlight the challenges that still remain to enable fully functioning, yieldable chips at dimensions required for technology beyond 7nm.

A 7nm chip has 20 billion transistors in the space roughly the size of a fingernail. They’ll make their way into systems and devices, extending the capabilities – and Moore’s Law – to do ever-more demanding tasks in data analysis, cognitive computing, and whatever the next generation of mobile apps hold. The work presented at SPIE this year nudges the industry closer to patterning solutions that not only make the 7nm process more robust with single-expose EUV, they also enable further scaling to realize even more power/performance benefit for years to come.


Figure 3: Innovation on multiple aspects of the patterning process allows IBM to deliver a holistic patterning process capability of delivering the feature sizes needed beyond the 7nm node.
Other IBM Presentations at 2017 SPIE

Design intent optimization at the beyond 7nm node: The intersection of DTCO and EUVL stochastic mitigation techniques, Michael Crouse, Nicole Saulnier, Derren Dunn

Investigation of alternate mask stacks in EUV lithography, Martin Burkhardt

Decomposition of the TCC using non-coherent kernels for faster calculation of lithographic images, Alan Rosenbluth

Development of Ti containing hardmasks through PEALD deposition, Anuja De Silva

DSA patterning options for logics and memory applications, Charlie Liu

Electrical study of DSA shrink process and CD rectification effect at sub-60nm using EUV test vehicle, Cheng Chi

Reaching for the True Overlay in Advanced Nodes, Chiew-Seng Koay

Topcoat-free Strategies for Orientation Control of All-organic High-χBlock Copolymers, Dan Sanders

Identification and reliability sensitivity analysis of a correlated ground rule system (design arc), Eric Eastman

Advanced fast 3D DSA model development and calibration for design technology co-optimization, Kafai Lai

Unexpected Impacts of RIE Gases onto Lithographic Films, Martin Glodde

Electrical Test Prediction using Hybrid Metrology and Machine Learning, Mary Breton

Reducing LER in Si and SiN Through RIE Optimization for Photonic Waveguide Applications, Nathan Marchack

Directed Self-Assembly Patterning Strategies for Phase Change Memory Applications, R. Bruce

Materials characterization for process integration of multi-channel gate all around (GAA) devices, Raja Muthinti

Comprehensive analysis of line-edge and line-width roughness for EUV lithography, Ravi Bonam
 

Tony254

Village Elder
#3
@Sambamba lets look at your beloved printing or photolithography.

After designing the chip it is then printed. I looked at the printer maker in Holland, ASML Holding and a keen look shows that it is controlled and financed by the usual U.S companies : IBM, Apple, Intel and then you have Samsung and TSMC.

ASML make the printing machines for these companies above according to the designs they need. And Trump has stopped ASML from selling machines to China :

https://www.reuters.com/article/us-asml-holding-usa-china-insight-idUSKBN1Z50HN


Looking at 7 nanometer which you love so much, si naona ni IBM ndio iliunda!

It then flows from IBM to the rest of the companies e.g TSMC but the U.S companies own the science and the patents.

https://en.m.wikipedia.org/wiki/7_nm_process




HistoryEdit
Technology demosEdit

7 nm scale MOSFETs were first demonstrated by researchers in the early 2000s. In 2002, an IBM research team including Bruce Doris, Turkish engineer Omer Dokumaci, Taiwanese engineer Meikei Ieong and Romanian engineer Anda Mocuta fabricated a 6 nm silicon-on-insulator (SOI) MOSFET.[6][7] In 2003, NEC's research team led by Hitoshi Wakabayashi and Shigeharu Yamagami fabricated a 5 nm MOSFET.[8][9]

In July 2015, IBM announced that they had built the first functional transistors with 7 nm technology, using a silicon-germanium process.[10][11][12][13]

In June 2016, TSMC had produced 256 Mbit SRAM memory cells at their 7 nm process,[1] with a cell area of 0.027 mm2 (550 F2) with reasonable risk production yields.[14]





Looking at 5 Nanometer printing, again you see the same old names. No mention of China or Huawei :

https://en.m.wikipedia.org/wiki/5_nm_process



Technology demosEdit
Single-transistor devices below 7 nm were first demonstrated by researchers in the early 2000s. In 2002, an IBM research team including Bruce Doris, Omer Dokumaci, Meikei Ieong and Anda Mocuta fabricated a 6-nanometre silicon-on-insulator (SOI) MOSFET.[9][10]

In 2003, a Japanese research team at NEC, led by Hitoshi Wakabayashi and Shigeharu Yamagami, fabricated the first 5 nm MOSFET.[11][12]

In 2015, IMEC and Cadence had fabricated 5 nm test chips. The fabricated test chips are not fully functional devices but rather are to evaluate patterning of interconnect layers.[13][14]

In 2015, Intel described a lateral nanowire (or gate-all-around) FET concept for the 5 nm node.[15]

In 2017, IBM revealed that they had created 5 nm silicon chips,[16] using silicon nanosheets in a gate-all-around configuration (GAAFET), a break from the usual FinFET design. The GAAFET transistors used had 3 nanosheets stacked on top of each other, covered in their entirety by the same gate, just like FinFETs usually have several physical fins side by side that are electrically a single unit and are covered in their entirety by the same gate. IBM's chip measured 50 mm2 and had 600 million transistors per mm2.[17][18]
Huawei also owns alot of 5G patents. Huawei should also lock out American companies from using its technology.
 
#4
Huawei also owns alot of 5G patents. Huawei should also lock out American companies from using its technology.
Within this 5G technology you speak off kwani whose microchips and designs do they use?

If you look at a Huawei 5G router or modem or base station etcetera si utapata tu U.S technology.
 

Tony254

Village Elder
#5
Within this 5G technology you speak off kwani whose microchips and designs do they use?

If you look at a Huawei 5G router or modem or base station etcetera si utapata tu U.S technology.
Nilisoma mahali that around 20% of all patents on 5G globally are owned by Huawei. Those chips are not the only component of a base station. The chip is just one of the many components of a base station.
 
#6

Top